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MC74ACT640 Octal 3-State Inverting Transciever
The MC74ACT640 octal bus transceiver is designed for asynchronous two-way communication between data buses. The device transmits data from bus A to bus B when T/R = HIGH, or from bus B to bus A when T/R = LOW. The enable input can be used to disable the device so the buses are effectively isolated.
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* * * *
Bidirectional Data Path A and B Outputs Sink 24 mA/Source -24 mA TTL Compatible Inputs Pb-Free Packages are Available*
VCC 20 OE 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11
PDIP-20 N SUFFIX CASE 738 1
SOIC-20W DW SUFFIX CASE 751D 1
SOEIAJ-20 M SUFFIX CASE 967 1 1 T/R 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND
Figure 1. Pinout: 20-Lead Packages Conductors
(Top View)
ORDERING INFORMATION
Device MC74ACT640N MC74ACT640NG MC74ACT640DW MC74ACT640DWG MC74ACT640DWR2 Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) Shipping 18 Units/Rail 18 Units/Rail 38 Units/Rail 38 Units/Rail 1000 / Tape & Reel 1000 / Tape & Reel
PIN ASSIGNMENT
PIN A0-A7 OE T/R B0-B7 FUNCTION Side A Inputs or 3-State Outputs Output Enable Input Transmit/Receive Input Side B Inputs or 3-State Outputs
TRUTH TABLE
Applied Inputs X H L H L Valid Direction I/PO/P X A to B A to B B to A B to A MC74ACT640DWR2G Output X L H L H MC74ACT640MEL MC74ACT640MELG
OE H L L L L
T/R X H H L L
SOEIAJ-20 2000 / Tape & Reel SOEIAJ-20 2000 / Tape & (Pb-Free) Reel
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 4 of this data sheet.
1
December, 2006 - Rev. 3
Publication Order Number: MC74ACT640/D
MC74ACT640
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink/Source Current DC Supply Current per Output Pin DC Ground Current per Output Pin Storage Temperature Range Lead temperature, 1 mm from Case for 10 Seconds Junction temperature under Bias Thermal resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) PDIP SOIC PDIP SOIC (Note 1) Parameter Value *0.5 to )7.0 *0.5 v VI v VCC )0.5 *0.5 v VO v VCC )0.5 $20 $50 $50 $50 $50 *65 to )150 260 )150 67 96 750 500 Level 1 UL 94 V-0 @ 0.125 in > 2000 > 200 > 1000 $100 V Unit V V V mA mA mA mA mA _C _C _C _C/W mW
ILatchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf TJ IOH IOL Parameter DC Input Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Note 7) Junction Temperature (PDIP) Output Current - High Output Current - Low VCC = 4.5 V VCC = 5.5 V Min 4.5 0 -40 0 0 25 10 8.0 Typ Max 5.5 VCC +85 10 8.0 140 -24 24 Unit V V C ns/V C mA mA
6. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level. 7. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74ACT640
DC CHARACTERISTICS
TA = +255C Typ 1.5 1.5 1.5 1.5 4.49 5.49 TA = -405C to +855C Unit V V V V V V V V V V V V mA mA mA Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 mA *VIN = VIL or VIH IOH IOUT = 50 mA *VIN = VIL or VIH IOH VI = VCC, GND VI = VCC - 2.1 V VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VIN = VCC or GND -24 mA -24 mA -24 mA -24 mA
Symbol VIH
Parameter Minimum High Level Input Voltage
VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 0.5 5.0
VIL
Maximum Low Level Input Voltage
VOH
Minimum High Level Output Voltage
VOL
Maximum Low Level Output Voltage
4.5 5.5 4.5 5.5
0.001 0.001
0.1 0.1 0.36 0.36 0.1
IIN DICCT IOZ
Maximum Input Leakage Current Additional Max. ICC/Input Maximum 3-State Current
5.5 5.5 5.5 0.6
IOLD IOHD ICC
Minimum Dynamic Output Current Maximum Quiescent Supply Current
5.5 5.5 5.5 8.0
75 -75 80
mA mA mA
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 2 and 3.)
VCC* (V) An to Bn or Bn to An An to Bn or Bn to An OE to An or Bn OE to An or Bn T/R or OE to An or Bn T/R or OE to An or Bn 5.0 5.0 5.0 5.0 5.0 5.0 TA = +255C CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 8.0 8.0 10.0 10.0 10.0 10.0 TA = -405C to +855C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.5 9.0 11.0 11.0 11.0 11.0 Unit ns ns ns ns ns ns
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Propagation Delay Output Enable Time Output Enable Time Output Disable Time Output Disable Time
Parameter
*Voltage Range 5.0 V is 5.0 V 0.5 V
CAPACITANCE
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 15 45 Unit pF pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V VCC = 5.0 V
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MC74ACT640
SWITCHING WAVEFORMS
3.0 V T/R tr INPUT A or B 90% 50% 10% tPHL 90% 50% 10% OUTPUT A or B tTHL tTLH A OR B tPLH tf 3.0 V 3.0 V GND OE 50% GND tPZL tPLZ A OR B 50% tPZH tPHZ 50% 90% 10% HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE GND
Figure 2.
Figure 3.
450 W INPUT OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
MARKING DIAGRAMS
PDIP-20
SOIC-20W
SOEIAJ-20
20 20 MC74ACT640N AWLYYWWG 1 1 ACT640 AWLYYWWG
20 74ACT640 AWLYWWG 1
A WL YY, Y WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
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MC74ACT640
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SOIC-20W DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74ACT640
PACKAGE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC74ACT640/D

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